Analog Devices Blackfin Processor Family Embedded Software Solutions

Blackfin® Processor Development Tools

Green Hills Software provides a comprehensive set of development tools for Analog Devices Blackfin Processor based applications:

Optimizing C/C++ Compilers
ANSI C
K&R C
Embedded C++
Over 100 Advanced Optimizations
Inline Assembly
ELF/DWARF Output
Blackfin Processor ABI Compliant


MULTI® IDE (Integrated Development Environment)
Source Level Debugger
Graphical Project Builder
Text Editor
Version Control System
Performance Profiler
Run-Time Error Checking
Code Coverage Analysis
Instruction Set Simulator


The Green Hills Probe™

Run -Time LibrariesThe compiler distribution includes a comprehensive suite of run-time libraries for C and C++. Distributions include several different versions of the C++ libraries for Embedded C++ (EC++) with and without templates and exceptions. Full featured start-up code and libraries include automatic copy of data from ROM to RAM and system call emulation. Source code to the run-time libraries is available so that users can customize routines according to the special needs of their applications.Blackfin Processor Optimizing CompilersThe MULTI Integrated Development Environment for the Blackfin Processor includes both the Analog Devices VisualDSP++® compilers* (for highest performance on DSP algorithms) and Green Hills Optimizing compilers (for extended debugging capabilities and for highest reliability on large codebases).

The Green Hills Blackfin Processor Optimizing C and C++ compilers and tools support the following Blackfin Processor-specific features:Processor Options - One option for each supported Blackfin model.Constant Data Section - Places all string literals, constants, and initialized variables declared const in C and C++ in a distinct section.Hardware Loop Support - The Blackfin Processor compiler can generate nested hardware loops up to two levels deep.Circular Buffer Support - The Blackfin Processor compiler can generate circular pointer increments from intrinsic functions or directly from C code.ETSI Intrinsic Functions - The Blackfin Processor compiler supports a large number of ETSI intrinsic functions to allow the user fine control over fractional arithmetic. The intrinsic functions are recognized by the compiler, which generates very efficient Blackfin Processor code inline: often a single Blackfin Processor instruction carries out an ETSI intrinsic. The resulting instructions can be fully optimized by the compiler.Blackfin Intrinsic Functions - The Blackfin Processor compiler also supports a large number of powerful intrinsic functions based on the Blackfin Processor instruction set to allow the user direct access to specific Blackfin Processor capabilities. These instructions can be fully optimized by the compiler. *Windows onlyThe MULTI Integrated Development EnvironmentMULTI provides a host-based (Windows PC or UNIX workstation) graphical environment for Blackfin Processor target development. Host-target connectivity is provided through a variety of means, depending on the target environment. MULTI supports Blackfin Processor evaluation boards that can be accessed through: Bare Board Access (no RTOS or ROM Monitor) - MULTI supports on-chip debugging through JTAG. Multiprocessor-based boards are supported by the Green Hills Probe™, and Slingshot™ which let the MULTI debugger load, control, debug and test a target system without the need for prior board initialization, an RTOS, or even a ROM monitor.Custom RTOS Support - MULTI can be integrated with a custom RTOS through the Green Hills INDRT API. INDRT provides all the debug information needed by MULTI, and is easily integrated into custom kernel code.Multicore Debugging - A single instance of MULTI provides simultaneous debugging of multiple Blackfin Processor cores. MULTI can be adapted for multiprocessor debugging for Blackfin/MPU designs. Through MULTI’s intuitive graphical interface, users can: Debug each core or processor in a separate color-coded windowView and select cores or processors from a listSelect one or more cores or processors and assign them to a groupRun, step, or halt a single core or processor or the entire group